This week highlights the growing split between advanced-node AI momentum and mature-market stabilization.
Wafer demand is recovering, Europe is strengthening sub-2nm R&D, memory and HBM performance continue to surge, and AI infrastructure is driving both power innovation and design automation.
At the same time, legacy-node pricing pressure and inventory normalization remain visible across parts of the supply chain.
1. Silicon wafer shipments recover as AI drives 300mm demand
Global silicon wafer shipments grew 5.8% in 2025, reaching nearly 13,000 million square inches. Growth was led by strong demand for advanced 300mm wafers used in sub-3nm logic and high-bandwidth memory for AI accelerators and data centers.
However, total wafer revenue declined slightly, reflecting weaker pricing in mature-node segments such as automotive and consumer electronics. The market remains split between strong advanced-node momentum and slower legacy recovery.
2. Imec expands NanoIC pilot line for sub-2nm development
Imec opened a 2,000 m² cleanroom expansion in Leuven to support its NanoIC pilot line under the European Chips Act. The facility will focus on technology nodes beyond 2nm and will integrate High-NA EUV lithography in 2026.
The initiative brings together foundries, equipment makers, universities, and research institutions to accelerate advanced-node innovation and strengthen Europe’s semiconductor ecosystem.
3. QuTech introduces scalable architecture for spin qubits
Researchers unveiled QARPET, a tiled semiconductor spin-qubit platform designed to scale quantum processor development. The architecture supports more than 1,000 qubits using a crossbar configuration that reduces wiring complexity.
The platform enables statistical testing under real operating conditions, improving uniformity analysis and yield evaluation for future large-scale quantum systems.
4. Samsung begins commercial HBM4 shipments
Samsung started mass production of HBM4 for AI data center workloads. The new generation delivers up to 3.3 TB/s bandwidth per stack and improves power efficiency by roughly 40% compared to HBM3E.
HBM demand is expected to triple in 2026 as AI infrastructure continues to scale.
5. Navitas launches 10kW 800V AI datacenter power platform
Navitas introduced a high-efficiency 10kW DC-DC platform designed for 800V data center architectures. Using GaN technology, the system achieves up to 98.5% efficiency and supports migration toward higher-voltage AI power infrastructure.
The design targets improved power density and reduced copper losses in next-generation AI clusters.
6. OpenAI Codex-Spark runs on Cerebras wafer-scale systems
Cerebras announced a research preview of OpenAI’s Codex-Spark running on its wafer-scale engine. The model is optimized for real-time coding workflows and delivers very high inference throughput.
The focus is on ultra-low latency interaction, supporting agent-style development environments and faster iteration cycles.
7. Samsung joins Applied Materials’ $5B EPIC R&D center
Samsung Electronics will join Applied Materials’ new Equipment and Process Innovation and Commercialization Center in Silicon Valley.
The EPIC Center aims to reduce the time from early R&D to high-volume manufacturing by enabling tighter collaboration on next-generation materials and advanced-node scaling.
8. Marvell adds PCIe and CXL switching with XConn acquisition
Marvell completed its acquisition of XConn Technologies, expanding into PCIe and CXL switching for AI and cloud connectivity.
The move strengthens Marvell’s position in scale-up architectures where interconnect performance is becoming a bottleneck in multi-accelerator systems.
9. Cadence launches ChipStack AI Super Agent for design automation
Cadence introduced ChipStack AI Super Agent to automate front-end chip design and verification tasks. The system orchestrates RTL generation, testbench creation, regression flows, and debug support.
Early deployments suggest major productivity gains as design complexity increases and engineering bandwidth tightens.
10. Intel optimizes hybrid AI execution on AI PCs
Intel detailed work on hybrid execution models for AI assistants, splitting workloads between cloud and local AI PCs. Sensitive data remains on-device while external tasks leverage cloud models.
The approach aims to reduce cloud costs, improve privacy, and enable always-on AI assistants powered by Core Ultra processors.
